AMD K5

Historia

The K5 was developed by AMD to compete with Intels Pentium microprocessor range. Introduced in 1996 almost 2 years late, AMDs problems were compounded by being unable to manufacture the chip at the clock speeds originally projected. In its favor, the K5 did at least offer good x86 compatibility. All models had 4.3 million transistors on-chip. No K5 supported MMX instructions. Internally ambitious, it was closer to a Pentium Pro than a Pentium, based upon an internal highly parallel RISC processor architecture with an x86 decoding front-end. Improvements and differences to the Intel Pentium include: Five integer units, which could process instructions out of order, one floating point unit, compared to two units of the Pentium The branch target buffer was four times the size of the Pentiums, although not reportedly more accurate Register renaming improved parallel performance of the pipelines Speculative execution of instructions reduced pipeline stall The instruction cache is 16 Kb, double the Pentium The primary cache is 4-way set associative instead of the Pentiums 2-way The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation was weak. The low clock rates were due in part to AMDs deficiencies as a manufacturing company in the period. However, having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance, is an example of how the actual implementation fell short of the project goals. Additionally, while the K5s floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed. Overall, the chip failed to deliver, both in terms of raw performance, and financially for AMD.